An information handling system (IHS) may include multiple processors for processing, handling, communicating or otherwise manipulating information. Each processor may itself include multiple processor cores that work together to process information. A processor or processor core may include several pipeline stages to increase the effective throughput of the processor. Pipelining enables the processor or processor core to obtain greater efficiency by performing operations in parallel. The transition to multi-core processor designs tends to increase power dissipation issues in processors.
Total power consumption is now one of the major concerns in processor design such as multi-core processor design. Excessive processor power consumption can cause the processor to function improperly. Moreover, excessive power consumption without adequate heat dissipation can cause a processor to become unstable or permanently damaged. External cooling devices such as fans, coolers and radiators are effective up to a point in addressing the problem of high power dissipation and the resultant heat generation by high performance processors. Unfortunately, these devices are typically expensive and noisy. Moreover, these cooling devices are often bulky and require special design and packaging methods that are not desirable especially in portable or battery powered systems.
Power dissipation or consumption in processors includes two main aspects, namely leakage power dissipation and active power dissipation. Leakage power dissipation increases as semiconductor manufacturing processes shrink processor elements smaller and smaller. In contrast, active power dissipation relates mainly to the activity of the processor at a particular workload. For example, the activity of sequential elements such as latches is one cause of active power dissipation in processors. Data switching by combinational logic in the processor is another cause of active power dissipation. Latches in the pipeline stages of a processor cause a significant amount of power consumption. Latch-based elements include flip-flops, data storage logic, registers, switching components, and other components in the processor. Better control of latch-based element operations represents a significant opportunity for power reduction in a processor.
Latch clocking is a major component of the active portion of power consumption and dissipation in processors. Clocking a latch, whether the latch changes state or not, causes the latch to consume power. Reducing latch clock activity to reduce power consumption is desirable, but presents a major design challenge in complex processors. “Clock gating” achieves a significant reduction in latch clock power consumption. Clock gating is a technique that turns off or interrupts the clock signal to the clock input of a particular latch or set of latches under certain conditions without harm to latch functionality. A “clock-gated” latch is a term that describes a latch in a state wherein clock gating circuitry turns off or interrupts the latch's clock signal. Otherwise, the latch operates normally. A “clock-gated” latch will not actuate, toggle, or otherwise change state during the normal clock cycle input. This blocking of the clock signal input and the ensuing static state of the latch provides power savings for the processor. Determining when to clock gate a latch and when not to clock gate a latch presents a significant design challenge to the processor designer. Basically, it is acceptable to clock gate a latch during a particular clock cycle, when the state of the latch will not change during that particular clock cycle, or when the state change of the latch has no impact on subsequent downstream logic. However, making this determination of when to clock gate and when not to clock gate is the challenge. One approach to designing clock gating logic is to conduct a manual study to determine those times when the data in the latch is the same data present on the latch's input (i.e. Din=Qout). Simulation is also useful to determine clock gating opportunities. However, these approaches may be too pessimistic in assessing clock gating opportunities. Even after a designer carefully uses these design practices to generate clock gating logic for the processor, there are likely still complex scenarios that the designer may not fully investigate that could yield further clock gating opportunities.
What is needed is a design structure for an apparatus that more completely identifies clock gating opportunities in a pipelined electronic processor device.